National Education Society ®
JAWAHARLAL NEHRU NATIONAL COLLEGE OF ENGINEERING
Shivamogga - 577204
DEPARTMENT OF Electronics & Communication
LESSON PLAN
COURSECODE : 17EC63
COURSE TITLE : VLSI Design
HOURS DISTRIBUTION : 4hr/Week
PROGRAM/ BRANCH : Electronics & Communication
SEMESTER : VI ‘B’
Sec
ACADEMIC YEAR : 2019-20
FACULTY NAME : PRADEEPA S C
OBJECTIVES
OF COURSE:
At the end of
the Course, students should be able to:
·
Impart
knowledge of MOS transistor theory and CMOS technologies.
·
Impart
knowledge on architectural choices and performance tradeoffs involved in
designing and realizing the circuits in CMOS technology.
·
Cultivate
the concepts of subsystem design processes.
·
Demonstrate
the concepts of CMOS testing.
OUTCOME
OF COURSE: Student will
be able to
Course Outcomes
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At
the end of the course, students must be able to
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C311.1
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Understand the basic
concepts of VLSI design Process
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C311.2
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Apply the knowledge of fabrication
process in the design cycle of transistor with their working principles
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C311.3
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Analyze the scaling features of,
CMOS subsystem design and memory elements using MOS theory
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C311.4
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Design the given logic function with
the basic circuit concepts using stick diagrams and layout
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C311.5
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Design FPGA based system design
along with logic verification & testing process in VLSI design
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CO-PO-PSO
Mapping
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CO
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PO1
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PO2
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PO3
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PO4
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PO5
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PO6
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PO7
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PO8
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PO9
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PO10
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PO11
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PO12
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PSO1
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PSO2
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C311.1
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C311.2
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3
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3
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C311.3
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3
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3
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C311.4
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3
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3
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3
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2
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2
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3
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C311.5
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3
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3
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3
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2
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2
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3
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C311
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Justification to CO-PO -PSO matrix for the course
C311:
In the course VLSI DESIGN, all
the COs are mapped to PO1, PO2, PO3,PO5, PO9, PO10 and PO12 as the topics
provide basic engineering knowledge, problem analysis and design; development
of processes.
C311.1 has strong correlation
with PO1 to PO12
C311.2 has a strong correlation with PO1, as it focuses
more on the knowledge of fabrication process in the design cycle of transistor
with their working principles.
C311.3 has strong correlation
with PO2, which involves analyze the scaling features, CMOS subsystem design
and Memory elements using MOS theory.
C311.4 has strong correlation
with PO3, PO5, PO9, PO10 and PO12 which involves realizing the given logic
function with the basic circuit concepts using stick diagrams and layout.
Also, C311.5 maps to PO3, 5, 9
and 10 with strong correlation as it focus more on FPGA based system design
with logic verification.
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Sl.
No. |
Topics
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No. of Hrs/ Period
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Reference Books
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Method of teaching
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Module -1 BASIC MOS TECHNOLOGY and MOS TRANSISTOR
THEORY
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Introduction
to Semiconductors, Charge carriers, Doping, PN- junction diode
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1
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Chalk & Talk
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Introduction : A Brief History
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T1,T2
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MOS Transistors, MOS
Transistor Theory
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1
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T1,T2
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Chalk & Talk
and
PPT
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Ideal
I-V Characteristics
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1
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T1,T2
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Non-ideal I-V Effects
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1
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T1,T2
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DC
Transfer Characteristics
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2
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T1,T2
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Fabrication: nMOS Fabrication
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1
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T1,T2
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CMOS Fabrication [P-well
process, N-well process, Twin tub
process]
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1
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T1
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CMOS Fabrication [P-well
process, N-well process, Twin tub
process]
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1
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T1
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BiCMOS Technology
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1
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T1
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Total no. of
hours
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11
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Course outcomes: C311.1
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Module -2
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Explanation of
various MOS technologies (nMOS, CMOS) to design the Boolean expression.
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1
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T2,T3
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Chalk & Talk
and PPT
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MOS
and BiCMOS Circuit Design Processes MOS Layers, Stick
Diagrams
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1
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T1
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Design Rules and Layout
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1
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T1
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Design Rules and Layout
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1
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T1
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Design
Rules and Layout
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1
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T1
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Basic
Circuit Concepts: Sheet Resistance, Area Capacitances of Layers,
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1
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T1
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Standard Unit of
Capacitance, Some Area Capacitance Calculations
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1
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T1
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Delay Unit, Inverter
Delays
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1
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T1
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Delay Unit, Inverter
Delays
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1
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T1
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Driving Large Capacitive
Loads
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1
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T1
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Driving Large Capacitive
Loads
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1
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T1
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Total no. of
hours
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10
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Course outcomes: C311.2
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Beyond the syllubus: Explanation of
various MOS technologies (nMOS, CMOS) to design the Boolean expressions.
Group Activity: Design and Analyze the some basic circuits using open source tool
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Module -3
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Scaling
of MOS
Circuits : Scaling
Models & Scaling
Factors for Device Parameters
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1
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T2
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Chalk & Talk
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Scaling Models
& Scaling Factors
for Device Parameters
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1
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T2
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Chalk & Talk
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Some General
considerations
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1
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T2
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Chalk & Talk
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Illustration of
the Design Processes
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2
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T2
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Chalk & Talk
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Regularity
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1
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T2
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Chalk & Talk
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Design of
an ALU Subsystem
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2
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T2
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Chalk & Talk
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The Manchester
Carry-chain
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1
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T2
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Chalk & Talk
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Adder Enhancement
Techniques
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1
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T2
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Chalk & Talk
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Assignment- Assignments on above Topics
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Total no. of
hours
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10
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Course outcomes: C311.2
C311.3
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Module -4
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Subsystem
Design
: Some Architectural Issues, Switch
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1
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T3
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Chalk & Talk
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Gate(restoring
Logic
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1
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T3
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Chalk & Talk
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Parity Generators,
Multiplexers
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1
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T3
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Chalk & Talk
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The Programmable Logic
Array (PLA)
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1
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T3
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Chalk & Talk
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FPGA
Based Systems : Introduction,
Basic concepts
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1
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T3
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Chalk & Talk
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Digital
design and FPGA’s
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1
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T3
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Chalk & Talk
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FPGA
based System design
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1
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T3
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Chalk & Talk
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FPGA
architecture
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1
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T3
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Chalk & Talk
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Physical
design for FPGA’s
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2
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T3
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Chalk & Talk
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Assignment- Assignments
on above Topics
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Total no. of
hours
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10
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Course outcomes: C311.3,
C311.4
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Module -5
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Memory, Registers and
Aspects of system Timing: System Timing Considerations
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2
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T2
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Technical Talk
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Some commonly used
Storage/Memory elements
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3
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T2
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Introduction, Logic
Verification
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1
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T2
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Logic Verification
Principles
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1
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T2
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Manufacturing
Test Principles
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1
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T2
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Design
for testability
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2
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T2
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Total no. of
hours
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10
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Course outcomes: C311.4, C311.5
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Grand Total no. of Hours
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52
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Text Books:
1.
“Basic VLSI
Design”-
Douglas A. Pucknell & Kamran Eshraghian, PHI 3rd Edition (original Edition – 1994). (T1)
2.
“CMOS VLSI
Design- A Circuits and Systems Perspective”- Neil H.E. Weste, David Harris, Ayan Banerjee, 3rd
Edition, Pearson Education. (T2)
3.
“FPGA Based
System Design”- Wayne Wolf, Pearson Education, 2004, Technology and Engineering. (T3)
