module3

VLSI design is for 6TH SEM Students of VTU
MODULE 3 presentation/Notes 
DOWNLOAD HERE...https://drive.google.com/file/d/1GYds6GgH6yQbuBeRh4wQDgThynz-NuWb/view?usp=sharing

module2

VLSI design is for 6TH SEM Students of VTU
MODULE 2 presentation/Notes 
DOWNLOAD HERE...https://drive.google.com/file/d/1Ukwa5ILyCzZfwfYsfbaYy-VuQqz72Bte/view?usp=sharing

Introduction and module1

VLSI design is for 6TH SEM Students of VTU
MODULE 1 presentation/Notes 
DOWNLOAD HERE...https://drive.google.com/file/d/150sUt-tvdDg2g6FqTdqT5zu5z5YfHDOe/view?usp=sharing

Syllabus 

VLSI Design

B.E., VI Semester, Electronics & Communication Engineering

[As per Choice Based Credit System (CBCS) scheme]

Subject Code 17EC63                                                                                                CIE  Marks 40

Number of Lecture Hours/Week 04                                                               SEE Marks 60

Total Number of Lecture Hours 50 (10 Hours / Module)                               Exam Hours 03

CREDITS – 04

Module-1

Introduction: A Brief History, MOS Transistors, MOS Transistor Theory, Ideal I-V Characteristics, Non-ideal I-V Effects, DC Transfer Characteristics

(1.1, 1.3, 2.1, 2.2, 2.4, 2.5 of TEXT 2).

Fabrication: nMOS Fabrication, CMOS Fabrication[P-well process, N-well process, Twin tub process], BiCMOS Technology (1.7, 1.8,1.10 of TEXT 1). L1, L2

Module-2

MOS and BiCMOS Circuit Design Processes: MOS Layers, Stick Diagrams, Design Rules and Layout.

Basic Circuit Concepts: Sheet Resistance, Area Capacitances of Layers, Standard Unit of Capacitance, Some Area Capacitance Calculations, Delay Unit, Inverter Delays, Driving Large Capacitive Loads (3.1 to 3.3, 4.1, 4.3 to 4.8 of TEXT 1). L1,L2,L3

Module-3

Scaling of MOS Circuits: Scaling Models & Scaling Factors for Device Parameters

Subsystem Design Processes: Some General considerations, An illustration of Design

Processes, Illustration of the Design Processes- Regularity, Design of an ALU Subsystem, The Manchester Carry-chain and Adder Enhancement Techniques (5.1, 5.2, 7.1, 7.2, 8.2, 8.3, 8.4.1, 8.4.2 of TEXT 1). L1, L2, L3

Module-4

Subsystem Design: Some Architectural Issues, Switch Logic, Gate (restoring) Logic, Parity Generators, Multiplexers, The Programmable Logic Array (PLA) (6.1 to 6.3, 6.4.1, 6.4.3, 6.4.6 of TEXT1).

FPGA Based Systems: Introduction, Basic concepts, Digital design and FPGA’s, FPGA based System design, FPGA architecture, Physical design for FPGA’s

(1.1 to 1.4, 3.2, 4.8 of TEXT 3). L1,L2,L3

Module-5

Memory, Registers and Aspects of system Timing- System Timing Considerations, Some commonly used Storage/Memory elements (9.1, 9.2 of TEXT 1).

Testing and Verification: Introduction, Logic Verification, Logic Verification Principles, Manufacturing Test Principles, Design for testability (12.1, 12.1.1, 12.3, 12.5, 12.6 of TEXT 2). L1, L2, L3.

Text Book:

1. “Basic VLSI Design”- Douglas A. Pucknell & Kamran Eshraghian, PHI 3^rd Edition (original Edition – 1994).

2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H.E. Weste, David Harris, Ayan Banerjee, 3rd Edition, Pearson Education.

3. “FPGA Based System Design”-Wayne Wolf, Pearson Education, 2004, Technology and Engineering.

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